Integrated circuits are very complex devices that include multiple layers. Each layer may include conductive material, isolating material and/or semi-conductive materials. These various materials are arranged in patterns, usually in accordance with the expected functionality of the integrated circuit.
Commonly, an integrated circuit includes a substrate, multiple conductive layers (also known as metal layers) and multiple dielectric layers. Conductive layers usually include conductors made of conductive materials, whereas the conductors are separated by isolating or dielectric materials such as various oxides. The dielectric layers are located between the conductive layers in an interlaced manner. Conductors of distinct conductive layers may be connected to each other and/or to the substrate by conductive materials (termed contacts or vias) that pass through the dielectric layers to connect a conductor in one layer to a conductor in an adjacent conductive layer.
Manufacturing failures may affect the electrical characteristics of the integrated circuits. Some of these failures result from unwanted disconnections between various elements of the integrated circuits. These failures are known as “open”. Other failures result from unwanted connections between various elements of the integrated circuits. These failures may include unwanted connections between isolated conductors, unwanted connections between a conductor and the ground via the substrate. These failures are also known as “shorts”.
A well-known inspection technique is the “voltage contrast technique”. This technique usually includes a charging stage and an imaging stage (often combine in a single scan or pass of a charged particle beam). During the charging stage an electron beam can be directed onto a portion of a test structure (sometimes a large sized pad that can be relatively easily located). During the imaging stage an electron beam is scanned across the test pattern whereas voltage potential level of a scanned point is reflected by an intensity and/or an energy level of secondary electrons emitted from said point.
Voltage contrast techniques are described in various publications, including U.S. Pat. No. 6,445,199 of Satya et al., U.S. Pat. No. 6,448,099 of Iacoponi et al., and U.S. Pat. No. 5,959,459 of Satya et el., all three patents are incorporated herein by reference.
Test patterns may be formed on various substrates/objects, such as test wafers and product wafers. Various test structures are described in the above mentioned U.S. patents, and in U.S. Pat. No. 6,475,871 of Stine et al. and in U.S. Pat. No. 6,449,749 of Stine, said U.S. patents are all incorporated herein by reference.
Test wafers aid in integrated circuit manufacturing process monitoring. They are designed and fabricated such that defects and malfunctions that occur during the manufacturing of integrated circuits can be detected and localized when the test wafers are tested and/or inspected.
Scanning electron microscopes are operable to implement voltage contrast techniques. They usually direct a beam of about 10−9 Amperes towards a specimen to provide charging patterns that are imaged and processed. Each SEM is characterized by a voltage resolution level. Many prior art SEMs (usually those of the fab type SEMs) have a relatively low voltage resolution (typically of 1Volts). Said low voltage resolution SEMs are utilized for detecting opens and shorts.